Logic cores are generally used as building blocks in creating electronic circuit designs. A logic core is a design that when implemented in hardware performs a predetermined function and which has input and output signal lines that can be connected to other logic. Example logic cores include digital filters and multipliers.
The traditional tools for creating logic cores generally support design entry via schematics or a hardware description language such as Verilog or VHDL. In addition, there are a multitude of proprietary languages for creating logic cores that are specifically suitable for a particular family of devices. These types of designs are sometimes termed “static” designs because once a device is configured and power is applied, the circuit remains the same until power is removed.
Circuit designs, including run-time parameterizable (RTP) logic core generators, can be created in the JBits™environment from Xilinx. The JBits environment is a Java-based tool that includes an application programming interface (API) that allows designers to develop logic and write a configuration bitstream directly to a Xilinx FPGA. The JBits API permits the FPGA bitstream to be modified quickly, allowing for fast reconfiguration of the FPGA. In a run-time reconfiguration system, circuits are configured and then reconfigured based on information supplied in real-time by user software, user data, or sensor data. With Virtex™FPGAs, the JBits API can be used to partially or fully reconfigure the internal logic of the hardware device. The JBits environment also supports run-time reconfiguration of FPGAs and also configuration of FPGAs over a communications network, for example, an intranet or the Internet.
Run-time reconfigurable systems are generally co-processor systems. A host processor executes a run-time reconfiguration program, and the run-time reconfiguration program implements application functions on the host processor, defines a circuit design, creates configuration data, and configures the FPGA.
The different design flows for static versus run-time reconfigurable designs has limited the extent to which RTP cores are used in conjunction with static designs. Without a way to easily combine static and RTP cores, designers are left to create designs in one form or the other. Thus, designers may be left to choose between the many static-design logic cores that are commercially available and the benefits of run-time parameterizable logic cores.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.